Flash memory is devised to have the advantages of both erasable programmable read only memory (EPROM) and electrically erasable PROM (EEPROM). Accordingly, flash memory provided electrical data programming and erasing and low manufacturing cost due to simple manufacturing process and small chip size.
While flash memory is a non-volatile semiconductor memory in which data is not destroyed by power interruptions, flash memory also has a property of random access memory (RAM) in that programming and erasing of information can be easily performed electrically in a system. Due to its advantages, flash memory is used in memory cards, which are memory devices substituting for a hard disks of portable office automation instruments, and so on.
Flash memory is programmed with data through the injection of hot electrons. That is, when hot electrons are generated in a channel due to potential difference between a source and a drain, some electrons that obtain energy of equal to or more than 3.1 electron-volt (eV), which is a potential barrier between a gate poly silicon and an oxide, move to and are stored in a floating gate by a high electric field applied to a control gate.
Therefore, while a conventional metal-oxide semiconductor (MOS) device is designed to restrain hot electrons because hot electrons may cause inferiority of the device, a flash memory device is designed to generate such hot electrons.
Core elements of a flash memory cell include a tunneling silicon oxide, a floating gate, a dielectric film (Oxide/Nitride/Oxide; ONO), and a control gate. The tunneling silicon oxide serves as a pathway of electrons and holes of a silicon substrate to the floating gate.
Now, a conventional flash memory structure is described with reference to FIGS. 1a-1e. 
Referring to FIG. 1a, a tunneling oxide layer 2 is grown by thermal oxidation of a silicon substrate 1. The tunneling oxide layer 2 serves as a pathway of electrons accelerated by an electric field to enter into the floating gate, which will be described later, when the electric field is applied. When the electric field is not applied, the tunneling oxide layer 2 plays a role of blocking electrons entered into the floating gate not to recur to the silicon substrate 1.
Next, a floating gate poly silicon layer is deposited to form a floating gate 3. The floating gate 3 plays a role of storing electrons. It is called to be programmed (memorized) when electrons are charged and to be deleted (removed) when electrons are discharged to the substrate 1.
Referring FIG. 1b, a dielectric layer 4 is formed on the floating gate 3 to have a layered structure of oxide/silicon nitride/oxide.
Subsequently, as shown in FIG. 1c, a control gate poly silicon layer 5 that serves as a substantial electrode is deposited on the dielectric layer 4.
Subsequently, a photoresist pattern is formed and a photolithography and etching process for gate defining are performed to etch the control gate layer 5 and the dielectric layer 4, the floating gate layer 3, and the tunneling oxide layer 2 simultaneously to form a gate 6 as shown in FIG. 1d. 
Finally, referring to FIG. 1e, an oxidation process is performed to the defined gate 6, which remains after etching, to perform oxidation of surrounding area of the defined gate 6. A silicon nitride layer is deposited and etched without a separate photolithography process to form a sidewall 7. An ion implanting process for forming a source 8 and a drain 9 is then performed.
However, according to the above conventional technique, overall topography of a wafer becomes complicated because both the floating gate and the control gate are formed on the surface of the silicon substrate by deposition.
To perform a planarization for reducing the height difference, a thickness of an insulating layer should be large. In most cases, the insulating layer over a transistor experiences heat treatment, and stress difference of the insulating layer itself is severely generated. Therefore, stress difference between after and before heat treatment becomes larger as the thickness of the insulating layer becomes larger.
Large changes in stress between before and after heat treatment causes stress-induced damage to the wafer. Such damage may include metal peeling or leakage current influencing the transistor thereunder.
Moreover, because the insulating layer is deposited thick, a large amount of the insulating layer should be removed by chemical mechanical polishing (CMP). According to the characteristic of CMP, planarization quality becomes inferior as the amount of the insulating layer to be removed increases, which means local topography can be caused.
Topography after CMP causes unequal contact resistance in a wafer, which decreases wafer yield.
Prior arts dealing with a subject matter of a semiconductor device having a gate in a trench include the following U.S. Patents.
U.S. Pat. No. 5,258,634 discloses an EPROM including a control gate arranged inside a trench and a floating gate and a manufacturing method thereof, U.S. Pat. No. 5,736,765 discloses an EEPROM which is able to decrease leakage current and improve topography by forming a trench to source and drain areas and forming a gate inside the trench and a manufacturing method thereof, U.S. Pat. No. 6,586,800 discloses a metal oxide semiconductor field-effect transistor (MOSFET) or ACCUFET having double trench gate, U.S. Pat. No. 5,770,514 discloses a vertical FET having a trench gate and a manufacturing method thereof, U.S. Pat. No. 6,420,249 discloses an EEPROM having a floating gate deposited by self-alignment, U.S. Pat. No. 6,580,119 discloses a FET having floating gate electrodes arranged linearly on a surface of a substrate between trenches and source/drain areas arranged as a pair between the floating gate electrodes, and so on.